*job id*:jr0203709
*job category*:engineering
*primary location*:guadalajara, jal mx
*other locations:
*job type*:college grad
atom logic design engineer
*as an rtl design engineer, your responsibilities include*:
- developing designing and delivering rtl for high performance, power, area efficient cpu ip.
- analyzing multiple micro architecture and implementation options to find the optimal design point considering power, performance, area, cost trade offs.
- developing a functional block unit rtl model, then integrating and validating.
- planning and directing physical implementation and block integration.
- skills at using sound methods and data to test new ideas as well as the desire to have your own ideas be challenged by others.
- skills to develop an implementation, plan, monitor, key indicators, and adjust resources and scope to deliver value on schedule.
- strong verbal and written communication and collaboration skills.
*qualifications*
*education*:
bachelor's in computer engineering, electrical engineering, or related field of study ("cedula profesional" may be required) with 1+ years of experience (experience can be offset by master's or phd degree)
relevant experience can be obtained through school work, classes and project work, internships, and/or work experience.
*minimum qualifications*:
- 1+ years of experience in rtl level digital ic design using system verilog and/or verilog.
- 3+ months of experience in low power design.
- intermediate+ english level.
*preferred qualifications*:
- master's degree in computer engineering, or electrical engineering.
- pre-silicon and post-silicon validation.
- analog design concerns and driving to an optimal solution between analog and digital designs.
- micro-architecture trade-offs and documentation.
- power management and upf.
- low-power design using upf and clock gating.
- multiple clock domain design.
- state machine design.
- simulation and debug experience using vcs/verdi.
- synthesis and speed path debug.
- scripting in an interpreted language eg: tcl, perl, python, ruby.
- knowledge/experience with formal property verification.
*inside this business group*
in the design engineering group (deg), we take pride in developing the best-in-class socs, cores, and ips that power intel's products.
from development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of moore's law and groundbreaking innovations.
deg is intel's engineering group, supplying silicon to business units as well as other engineering teams.
as a critical provider of all intel products, deg leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.