We are looking for motivated engineers with static timing analysis skill; good knowledge on timing convergence and corner definition in advanced tech nodes.
if you have expertise in this area and are excited by driving leading edge semiconductor technologies that make a difference in this world, this is the opportunity for you.
in this highly visible role, the candidate is expected to coordinate with 100+ engineers, work across multiple design teams in the usa and beyond, and collaborate with external companies/vendors while juggling various tech node issues concurrently.
experience in various sta tools, timing signoff margin development, timing signoff corner development, full chip timing closure, tape-out, and post-silicon analysis is an excellent skill to have in this position.
as an asic timing analysis engineer, you will be responsible for all aspects of timing including defining corners, helping construct and/or modify flows, ppa improvement, timing bottleneck analysis, and timing closure.
key qualifications:
* play a vital role in timing analysis targeting the mobile, compute, automotive, and iot markets.
* work with physical design on timing closure, cad teams, ip teams, and design technology teams for flow scripts/tools development and validation.
* facilitate and drive sta methodology using primetime, tempus, and best-in-class timing eco tools. In-depth knowledge of industry sta tools is key to this role.
* understand intricate timing paths (digital, analog, mixed signal), timing constraints, and provide solutions if required. Good understanding of rtl to gds digital flow is required.
* familiarity with timing closure of high-performance, mixed-signal socs in sophisticated process technology nodes (40nm to 3nm).
* good physical design execution knowledge (synthesis to timing sign off). Knowledge of low-power techniques including clock gating, power gating, and multi-voltage designs is required.
* good programming skills in python, perl, tcl, and unix shell. Expertise is required for the development of scripted automation for data processing related to timing convergence.
* ability to work and coordinate with large design teams is a must.
* timing signoff experience is a plus.
* ip design experience is a plus.
* excellent communication skills.
* excellent multitasking skills.
* above all, you should be a good team player with the ability to remain calm in challenging technical discussions, demanding customers, and schedule pressure.
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