Job description
join the cad team at qualcomm and advance the industry state of the art for dft. Support the company-wide deployment of flows architected to enable leading process nodes. Work closely with cross-functional teams from design, production test and yield analysis.
responsibilities
* will be part of dftcad automation team, developing methodology and flows to support end-2-end dft/dfx solution, and provide support and training.
* collaborate with soc design, product and test engineer teams to drive standardization of dft/atpg methodology and flow across the company.
* work closely with multiple eda tool vendors to resolve day-to-day issues, helping to drive vendor solutions.
* collect and evaluate requirements with consideration of improving design flow efficiency, test quality, and lower test cost to improve dft flow and methodology.
qualifications
* 3+ years of experience in dft/dfd/dfx, ms or phd degree in ee or related field, or equivalent experience.
* core dft skills for this position include: scan insertion, memory bist implementation, jtag/ijtag, at-speed test, atpg, fault simulation, silicon diagnostic, scan compression, idl/pdl, ssn, seq, core-based test methodology and io wrapping, pattern retargeting.
* experience developing automation for dft flow and architecting the dft methodology.
* strong coding experience with hands-on experience using tcl, python/perl, scripting, and strong analytical debug and problem-solving skills.
* good exposure to industrial dft tools including siemens, synopsys or equivalent.
* deep understanding of soc design, low power, timing exceptions, and complex clock structures.
* strong analytical and debugging experience for atpg drc, product manufacturing pattern failures, and design for debug concept and implementation.
* excellent team spirit, strong ownership and openness, highly motivated.
#j-18808-ljbffr