*required skills*:
- soc bandwidth, qos, latency and throughput analysis
- interconnect architectures - nocs, axi, ahb etc.
knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage
- solid expertise in various fifo designs and related performance/functionality aspects
- come up with thorough performance validation plans and work closely with team members to ensure performance-power trade-offs are factored in
- low power modes
- dynamic clock and voltage scaling operations
- interrupt architecture
- debug architecture - interactions with jtag based debuggers, state dump scripts
- performance monitor architecture
- thorough understanding of cpu and ddr concepts, multimedia, gpu, peripheral,
- memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, mte, mpam
- experience in embedded systems/expertise in c, c++, python and assembly languages
- design and implementation of drivers and test content
- debugging low level software and hardware issues
- familiarity in debug tools including jtag and kernel debuggers
- structured program development concepts
- understanding of performance metrics, testing methodologies
- design and implement performance validation tests for new and existing products.
- analyze and interpret test results and provide detailed reports on performance metrics.
- collaborate with cross-functional teams to identify and resolve performance issues.
- develop and maintain performance testing tools and frameworks.
*minimum qualifications*:
- bachelor's degree in science, engineering, or related field and 5+ years of asic design, verification, or related work experience.
or
master's degree in science, engineering, or related field and 4+ years of asic design, verification, or related work experience.
or
phd in science, engineering, or related field and 3+ years of asic design, verification, or related work experience.